PCB Design Questions

We get asked many PCB Design questions and noticed a trend in the questions we are asked about most frequently.  Do you have the same questions?  Please give us a call if we can help! 


Annular Ring/Pad size That portion of conductive material completely surrounding a hole.  This can be particularly confusing when working with IPC Class 2 vs. Class 3 and with space constraints. 


Aspect Ratio A ratio of the PCB board thickness to the diameter of the smallest hole.  This can be confusing when moving to a micro via construction.


Blind Via A conductive surface hole that connects an outer layer with an inner layer of a multi layer board without penetrating the entire board.


Buried Via – A via hole that connects two or more inner layers but does not extend to either surface of a printed board.


Micro via – Usually defined as a conductive hole with a diameter of 0.006″ or less that connects layers of a multilayer PCB. Often used to refer to any small geometry connecting hole, that is beyond the traditional mechanical drilling capabilities.  Micro via designs are increasing.  There is a whole new set of design rules and options available often with significant cost differences.


Controlled Impedance –  The matching of substrate material properties with trace dimensions and locations to create specific electric impedance as seen by a signal on the trace.  It is always a good idea to have your supplier verify this calculation for you early in your design process. 


Wrap Plating – Copper plating from the hole that wraps around the surface to increase via in pad reliability in the field.


HDI (High Density Interconnect) – Ultra fine-geometry multi layer PCB constructed with conductive surface micro via connections between layers. These boards also usually include buried and/or blind vias and are made by sequential lamination. Again, design rules can be confusing and different design approaches can have a significant impact on cost.


Interconnect Stress Test– The IST system is designed to quantify the ability of the total interconnect to withstand thermal and mechanical strains.  The test applies stress from the “as manufactured” state until the product reaches the point of interconnect failure.   


Back Drilling – The process of removing the unused portion “stub” of vias by drilling a larger hole from one or both sides after the plating processes. This is typically required in very high speed applications (10GHz or greater) to minimize the parasitic effects of the via stubs.



As always, please contact us for more information.  Designing and purchasing printed circuit boards should not be difficult!



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